AS4C128M8D3LB-12BCN

Alliance Memory
913-A4C1288D3LB12BCN
AS4C128M8D3LB-12BCN

Mfr.:

Paglalarawan:
DRAM DDR3, 1G, 128M x 8, 1.35V, 78-ball BGA, 800MHz, (B die), Commercial Temp - Tray

Datasheet:
ECAD Model:
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May Stock: 29

Stock:
29 Maaaring Ipadala Agad
Lead-Time ng Pabrika:
8 (na) Linggo Tinatayang oras ng paggawa sa pabrika para sa mga bilang na mas marami kaysa ipinakita.
Minimum: 1   Mga Multiple: 1
Presyo ng Unit:
₱-.--
Ext. Presyo:
₱-.--
Est. Taripa:

Presyo (PHP)

Dami Presyo ng Unit
Ext. Presyo
₱538.82 ₱538.82
₱501.70 ₱5,017.00
₱486.04 ₱12,151.00
₱474.44 ₱23,722.00
₱448.92 ₱44,892.00
₱436.74 ₱105,691.08
₱426.88 ₱206,609.92
₱418.76 ₱405,359.68
2,662 Quote

Katangian ng Produkto Value ng Attribute Pumili ng Attribute
Alliance Memory
Kategorya ng Produkto: DRAM
RoHS:  
SDRAM - DDR3L
1 Gbit
8 bit
800 MHz
FBGA-78
128 M x 8
225 ps
1.283 V
1.45 V
0 C
+ 95 C
AS4C128M8D3LB
Tray
Brand: Alliance Memory
Bansa ng Pag-assemble: Not Available
Bansa ng Diffusion: Not Available
Bansang Pinagmulan: TW
Maselan sa Moisture: Yes
Isitilo ng Mounting: SMD/SMT
Uri ng Produkto: DRAM
Dami ng Pack ng Pabrika: 242
Subcategory: Memory & Data Storage
Supply Current - Max: 72 mA
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Mga Piniling Attribute: 0

Datasheet

CAHTS:
8542320020
USHTS:
8542320032
MXHTS:
8542320201
ECCN:
EAR99

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.

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