IM5116D2DDBG-25

Intelligent Memory
822-IM5116D2DDBG-25
IM5116D2DDBG-25

Mfr.:

Paglalarawan:
DRAM DDR2 512Mb, 1.8V, 32Mx16, 400MHz (800Mbps), 0C to +95C, FBGA-84

ECAD Model:
I-download ang libreng Library Loader para i-convert ang file na ito para sa iyong ECAD Tool. Matuto nang higit pa tungkol sa ECAD Model.

Availability

Stock:
0

Mabibili mo pa rin ang produktong ito para sa backorder.

Lead-Time ng Pabrika:
8 (na) Linggo Tinatayang oras ng paggawa sa pabrika para sa mga bilang na mas marami kaysa ipinakita.
Minimum: 1   Mga Multiple: 1
Presyo ng Unit:
₱-.--
Ext. Presyo:
₱-.--
Est. Taripa:

Presyo (PHP)

Dami Presyo ng Unit
Ext. Presyo
₱226.20 ₱226.20
₱211.12 ₱2,111.20
₱204.74 ₱5,118.50
₱200.10 ₱10,005.00
₱190.24 ₱19,024.00
₱185.02 ₱38,669.18
₱182.12 ₱76,126.16
₱179.22 ₱187,284.90
₱177.48 ₱445,119.84

Katangian ng Produkto Value ng Attribute Pumili ng Attribute
Intelligent Memory
Kategorya ng Produkto: DRAM
RoHS:  
SDRAM - DDR2
512 Mbit
16 bit
400 MHz
FBGA-60
32 M x 16
400 ps
1.7 V
1.9 V
- 40 C
+ 95 C
IM5116D2
Tray
Brand: Intelligent Memory
Bansa ng Pag-assemble: Not Available
Bansa ng Diffusion: Not Available
Bansang Pinagmulan: TW
Maselan sa Moisture: Yes
Isitilo ng Mounting: SMD/SMT
Uri ng Produkto: DRAM
Dami ng Pack ng Pabrika: 209
Subcategory: Memory & Data Storage
Supply Current - Max: 90 mA
Timbang ng Unit: 154 mg
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Mga Piniling Attribute: 0

CAHTS:
8542320020
USHTS:
8542320028
MXHTS:
8542320299
ECCN:
EAR99

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.